1. Field of the Invention
The present invention relates to a first-in first-out buffer memory adapted for high speed operation and high-density integration.
2. Description of the Prior Art
First-in first-out (hereinafter, referred to as "FIFO") buffer memory is a memory unit that stores information in such a manner that the item first in is the item first out. A FIFO buffer memory is provided with separate input and output terminals, i.e. a dual port. This buffer memory has two important features, one of which is that it can input data and output data at two different rates, the other of which is that the output data are always in the same order in which the data are entered the buffer memory. When placed between two units having different data transfer rates, the FIFO buffer memory can accept data from the source unit at one rate of transfer and deliver the data to the destination unit at another rate. If the source unit is slower than the destination unit, the buffer memory can be filled with data at a slow rate and later emptied at the higher rate. If the source unit is faster than the destination unit, the buffer memory is useful those cases where the source data arrives in bursts that fill out the buffer but the time between bursts is long enough for the destination unit to empty some or all the information from the buffer. Thus, a FIFO buffer memory can be useful in some applications when data is transferred asynchronously.
For example, if there is no FIFO buffer memory between two units having different rates of transfer and a direct connection is made between them, there is a problem on an interface therebetween that the source unit waits to receive data from the destination unit until the destination unit completes its working job. In order to eliminate the problem, a FIFO buffer memory is frequently used between the two units to achieve a time buffering function therebetween.
FIG. 1A shows a relationship between a prior art FIFO buffer memory and system clock signals for data transfer. As shown in FIG. 1A, since the FIFO buffer memory has a dual port, read and write operations are simultaneously performed while one of the clock system signals is activated. Because of this reason, the FIFO buffer memory has been used in some applications. For example, the FIFO buffer memory may be used in the interface apparatus between systems, the interface apparatus between block units having different rates of transfer, an apparatus for transforming serial data into parallel data, an apparatus for transforming parallel data into serial data, or the like. Also, it can be seen from FIG. 1B that, in the FIFO buffer memory, the write operation is performed during a leading edge (i.e. rising edge) of the clock signal as one of non-data signals and the read operation is performed during a trailing edge (i.e. falling edge) of the clock signal.
FIG. 2 is an overall block diagram showing the construction of a prior art FIFO buffer memory shown in FIG. 1.
Referring to FIG. 2, the FIFO buffer memory comprises a core memory 1 having a dual port, for substantially storing a binary-coded information (hereinafter, referred to as "data"), address counters 5 and 6 for producing addresses directing locations in the core memory 1 when writing of data to the core memory or reading of data from the core memory is performed, and a flag generator 7 for generating memory status flags. The addresses are provided as read and write addresses to the core memory 1. In the prior art FIFO buffer memory, the flag generator 7 and the address counters 5 and 6 constitutes a control logic 4. The flag generator 7 generates two flags indicative of conditions of memory status, one of which is a full flag indicating that the core memory 1 is full and can not input additional data, and the other of which is an empty flag indicating that the core memory 1 is not full, i.e. empty, and can input the additional data. As the core memory 1, registers or SRAM's (Static Random Access Memories) are mainly used, because the FIFO buffer memory is provided with a collection of storage registers, together with the associated circuits needed to transfer information in and out of the registers.
FIG. 3 is a detailed circuit diagram of the control logic 4 shown in FIG. 2.
With reference to FIG. 3, the flag generator 7 has address registers 8 and 9 for temporarily storing address signals supplied from the counters 5 and 6, respectively, a comparator 10 for comparing the output of the write address counter 5 with the output of the read address register 9 to output the full flag and another comparator 11 for comparing the output of the read address counter 6 with the output of the write address register 8 to output the empty flag. Thus, the status of the FIFO buffer memory can be indicated by the full and empty flags.
However, since the prior art FIFO buffer memory is provided with address counters, address registers and comparators, as shown in FIGS. 2 and 3, there are some problems that a size thereof is larger and thus an operating speed thereof is lowered.
Particularly, in case that the number of memory addresses is increased in the FIFO buffer memory, the control logic 4 embodied in the buffer memory is complicated. This causes the same problems as those of low operating speed and larger size thereof.